RTL / Digital IC Design Engineer (Junior / Entry-Level)

Responsibilities Develop synthesizable RTL (Verilog/SystemVerilog) for DSP blocks and high-speed datapath logic used in ODSP and photonics ICs. Translate system and algorithm requirements into RTL micro-architecture including pipelines, datapaths, and control logic. Perform RTL simulation and debug functionality using testbenches and waveform analysis. Contribute to high-throughput, low-latency datapath design with awareness of timing, power, and area constraints. Collaborate with DV engineers …