Senior Digital Verification Engineer

Senior Digital Verification Engineer Responsible for end-to-end verification ownership of complex digital and mixed-signal designs, from block level to full chip and system-level verification. You will work closely with digital design, analog/mixed-signal, firmware, and system teams, applying state-of-the-art verification methodologies to ensure robust, first-pass silicon success. Responsibilities: Own block-level, chip-level, and system-level verification. Develop comprehensive verification plans, including test strategy, functional coverage, assertions, and closure criteria. Build and maintain UVM-based verification environments from the ground up. Drive functional coverage, code coverage analysis, and closure, ensuring verification completeness and quality. Perform in-depth debug and root-cause analysis of complex functional and integration issues. Work closely with digital design teams during architecture definition and RTL development to enable effective verification. Collaborate with analog/mixed-signal teams on co-simulation and mixed-signal verification strategy. Partner with firmware/software teams to enable system-level and application-level verification. Support post-silicon validation and bring-up, working with product evaluation and applications engineering teams. Requirements: B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or related fields. 3+ years of hands-on experience in digital verification for complex SoC designs (senior-level expectations). Strong expertise in SystemVerilog and UVM, including testbench architecture, sequences, scoreboards, assertions, and coverage. Solid experience with functional coverage, code coverage analysis, and coverage-driven verification. Familiarity with AMBA protocols such as AXI, AHB, and APB, and verification of processor-based SoCs. Proficiency in SystemVerilog, C/C++, and scripting languages such as Python, Perl, Tcl, or shell scripting. Strong debugging, analytical, and problem-solving skills. Experience in mixed-signal verification, analog modeling, or co-simulation is a strong plus. Experience or awareness of AI-assisted tools to improve design productivity is a plus. Experience with post-silicon validation or close interaction with silicon bring-up teams is a plus. Self-motivated, able to work independently, and comfortable driving tasks with minimal supervision. Good spoken and written English communication skills.