About this role
Responsible for the design and verification of blocks using leading-edge methodology and tools. The role focuses on high-performance compute and networking standards in advanced CMOS process nodes.
Requires a background in EE/CS with a focus on VLSI or Computer Architecture and proficiency in RTL design languages like Verilog. Familiarity with verification methodologies such as UVM and scripting languages like Python is required.
What they're looking for
Analog LayoutMixed-Signal LayoutVLSIComputer ArchitectureVerilogSystem VerilogUVMPython
Frequently asked questions
What does a Analog / Mixed-Signal Layout Engineer at Astera Labs do?
Responsible for the design and verification of blocks using leading-edge methodology and tools. The role focuses on high-performance compute and networking standards in advanced CMOS process nodes. Requires a background in EE/CS with a focus on VLSI or Computer Architecture and proficiency in RTL de…
What skills does this Analog / Mixed-Signal Layout Engineer role need?
Key skills for this role include Analog Layout, Mixed-Signal Layout, VLSI, Computer Architecture, Verilog, System Verilog.
How much does a Analog / Mixed-Signal Layout Engineer at Astera Labs pay?
The employer did not list a salary for this role. Most similar Singapore roles publish their band on the job page.
Is this Analog / Mixed-Signal Layout Engineer role remote, hybrid, or on-site?
This role is on-site, based in Singapore.
How do I apply for this Analog / Mixed-Signal Layout Engineer role?
You can apply directly on Astera Labs's careers page. ApplyLah can tailor your résumé and cover letter to this exact role in seconds first.