About this role
Responsible for integrating commercial RISC-V core soft IP with external accelerators and tailoring microarchitecture to meet PPA requirements. The role involves RTL modifications to the processor front-end and driving ASIC implementation steps including synthesis and timing closure.
Requires a degree in Electrical Engineering, Computer Engineering, or Computer Science with a strong focus on computer architecture and RISC-V expertise. Candidates must have extensive experience in Verilog RTL development and collaboration across performance and physical design teams.
What they're looking for
RISC-V ISAVerilogSystemVerilogCPU ArchitectureRTL DesignASIC Front-EndStatic Timing AnalysisSynthesis
Frequently asked questions
What does a Senior/Staff Front-End Design Engineer (RISC-V) at Bitdeer Technologies Group do?
Responsible for integrating commercial RISC-V core soft IP with external accelerators and tailoring microarchitecture to meet PPA requirements. The role involves RTL modifications to the processor front-end and driving ASIC implementation steps including synthesis and timing closure. Requires a degr…
What skills does this Senior/Staff Front-End Design Engineer (RISC-V) role need?
Key skills for this role include RISC-V ISA, Verilog, SystemVerilog, CPU Architecture, RTL Design, ASIC Front-End.
How much does a Senior/Staff Front-End Design Engineer (RISC-V) at Bitdeer Technologies Group pay?
The employer did not list a salary for this role. Most similar Singapore roles publish their band on the job page.
Is this Senior/Staff Front-End Design Engineer (RISC-V) role remote, hybrid, or on-site?
This role is on-site, based in Singapore.
How do I apply for this Senior/Staff Front-End Design Engineer (RISC-V) role?
You can apply directly on Bitdeer Technologies Group's careers page. ApplyLah can tailor your résumé and cover letter to this exact role in seconds first.