About this role
Develop and implement Verilog RTL for PCIe-related IP blocks and ensure full functional coverage for verification closure. Collaborate with software and verification teams to debug issues across pre-silicon and post-silicon stages.
Requires a Bachelor's or Master's degree in Electrical or Computer Engineering with at least 5 years of semiconductor R&D experience. Must possess strong expertise in PCIe architecture, Verilog RTL development, and scripting languages for automation.
What they're looking for
Verilog RTLPCIe ArchitectureLogic DesignPre-silicon DebuggingPost-silicon DebuggingPerlShellTCL
Frequently asked questions
What does a Senior/Staff Front-End Engineer (IP/PCIe) at Bitdeer Technologies Group do?
Develop and implement Verilog RTL for PCIe-related IP blocks and ensure full functional coverage for verification closure. Collaborate with software and verification teams to debug issues across pre-silicon and post-silicon stages. Requires a Bachelor's or Master's degree in Electrical or Computer E…
What skills does this Senior/Staff Front-End Engineer (IP/PCIe) role need?
Key skills for this role include Verilog RTL, PCIe Architecture, Logic Design, Pre-silicon Debugging, Post-silicon Debugging, Perl.
How much does a Senior/Staff Front-End Engineer (IP/PCIe) at Bitdeer Technologies Group pay?
The employer did not list a salary for this role. Most similar Singapore roles publish their band on the job page.
Is this Senior/Staff Front-End Engineer (IP/PCIe) role remote, hybrid, or on-site?
This role is on-site, based in Singapore.
How do I apply for this Senior/Staff Front-End Engineer (IP/PCIe) role?
You can apply directly on Bitdeer Technologies Group's careers page. ApplyLah can tailor your résumé and cover letter to this exact role in seconds first.