Package Development Engineer -Singapore

Team Introduction The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape-out, mass production, packaging, testing, and board-level verification. They collaborate closely with front-end chip teams across business units to drive R&D progress and mass production deployment for chip. Responsibilities 1. Provide chip packaging design solutions, including packaging selection, packaging design, packaging implementation, PinMap definition, and board-level interconnection. 2. Interface with chip designers and board-level designers to handle interface-related issues. 3. Responsible for signal integrity (SI) and power integrity (PI) analysis and optimization. Minimum Qualifications 1. Master's degree or above in Microelectronics, Electronics, Communications, Computer Science, or related fields, with at least 2 years of relevant work experience. 2. Proficiency in EDA tools in the packaging and PISI (Power Integrity & Signal Integrity) fields. 3. Experience in undertaking PISI work for complex SoC chips, including high-speed interfaces such as DDR, PCIe, and Serdes. 4. Familiarity with packaging structures, reliability, thermal performance, and various high-speed/high-frequency interface protocols. Preferred Qualifications 1. Strong teamwork spirit and a responsible work attitude. 2. Excellent communication skills, with fluent English reading and writing abilities.