Lpu Chip Architecture Engineer

Responsibilities Define the overall architecture of LPU chips based on a static dataflow architecture, including compute array design and on-chip SRAM memory hierarchy planning, to address latency and data movement challenges in large model inference. Collaborate with compiler engineers to define hardware microarchitecture and enable hardware-software co-design, ensuring efficient scheduling strategies before tape-out. Build architectural models to evaluate compute performance, memory bandwidth, latency, and power consumption, and benchmark LPU architecture against GPU and NPU architectures. Research the inference characteristics of MoE and multimodal foundation models, and continuously optimize the LPU architecture for next-generation AI workloads. Participate in front-end chip design, FPGA prototyping, chip bring-up, and performance validation. Investigate state-of-the-art AI accelerator architectures (e.g. Groq, Etched, Cerebras), and contribute to architecture evaluation and future design improvements. Qualifications PhD graduate in Microelectronics, Integrated Circuits, Computer Architecture, Computer Engineering, Electrical Engineering, or a related field. Solid understanding of computer architecture , AI accelerator architecture , static dataflow architecture , or systolic array architecture . Familiar with the inference workflow of large language models, including Prefill and Decode stages. Knowledge of memory hierarchy and on-chip SRAM optimization is a plus. Experience through research projects, FPGA implementation, or chip design projects involving AI accelerators, NPUs, GPUs, or related architectures. Familiar with computer architecture modeling, performance analysis, or architectural simulation methodologies. Strong programming skills (e.g. C/C++, Python) and familiarity with hardware design languages (Verilog/SystemVerilog) are preferred. Good communication skills and the ability to collaborate across architecture, compiler, and hardware design teams.