Physical Design Engineer

Company Overview JDI is a Venture Catalyst driving forward the future of innovation. We empower innovative companies to build, grow, and scale across Southeast Asia. 1) Tech JDI - Developing great tech solutions 2) Talent JDI – Growing human capital 3) Launch JDI – Accessing new markets 4) Capital JDI - Raising venture capital 5) Venture JDI - Building new ventures Our clients range from fast-scaling start-ups to MNCS as well as Unicorns from industries such as e-commerce, cybersecurity, Fintech, F&B, Edtech, etc. Job Purpose You will be responsible for the physical implementation of large-scale, high-performance ASICs ranging from 100M to 400M gates. This role involves taking complex designs from RTL/Netlist through to GDSII, ensuring all timing, power, and area (PPA) goals are met using advanced process nodes (7nm down to 2nm). Key Responsibilities Full-Flow Implementation: Execute the complete physical design flow, including Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), and Routing. Sign-off Verification: Perform physical verification (DRC/LVS/ERC) and Static Timing Analysis (STA) to ensure the design meets manufacturing requirements. Architecture Optimization: Work closely with front-end teams to implement CPU/DSP architectures, translating complex algorithms into optimized physical layouts. Advanced Node Management: Address challenges specific to 5nm, 3nm, and 2nm processes, such as multi-patterning, electromigration, and IR drop. Automation: Develop and maintain scripts to automate EDA tool flows and improve design productivity. Requirements Programming: High proficiency in Python, Tcl, and Shell scripting. Architecture Knowledge: Basic understanding of CPU/DSP data paths to better optimize tool placement algorithms. Environment: Advanced UNIX/Linux administration skills (managing disk space, memory, and LSF/Grid jobs). Degree: A Bachelor’s degree in Electrical Engineering (EE), Electronic Engineering, Computer Engineering (CE), or a closely related technical field is the mandatory baseline.