Analog Ic Design Engineer, Principal Engineer

Requirements Master’s degree and/or PhD Preferred in Electrical Engineering or related fields with 6+ years of experience. Should have strong analog design fundamentals and experience in designing analog circuit blocks such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.). Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution. Good understanding of analog layouts in FinFet and its effect on high-speed designs Experienced in system level pre-tape out analog validation Experienced in lab chip bring-up and debugging efforts Strong communication and documentation skills Technical management experience is a plus Job Responsibilities Analog circuit design, such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.). New technique development for next generation SERDES Project leading and management Analog layouts supervise with advanced process node System verification and circuit design spec creation Silicon bring-up, debug and support Team communication and documentation