About this role
The manager will lead a team supporting advanced 3D NAND development and production, focusing on releasing design rules and PDK deliverables, coordinating waivers, and owning program execution from kickoff to end-of-life. Responsibilities also include partnering with various engineering groups to guide new technology generations and ensuring high quality and documentation for Build Rule Checks.
Candidates need extensive experience in the semiconductor industry, requiring a PhD with 5+ years, Master's with 8+ years, or Bachelor's with 13+ years, specifically in areas like Process Integration or Yield Improvement. Essential technical requirements include direct experience with PDK, design rules, layout, CAD software (like Cadence Virtuoso), and a strong understanding of semiconductor device physics and 3D NAND process flow.
What they're looking for
Design RulesPDKDRC WaiversMask DefinitionsProgram ExecutionProcess IntegrationLayoutModeling
Frequently asked questions
What does a NAND Design Rule Manager at Micron Technology do?
The manager will lead a team supporting advanced 3D NAND development and production, focusing on releasing design rules and PDK deliverables, coordinating waivers, and owning program execution from kickoff to end-of-life. Responsibilities also include partnering with various engineering groups to gu…
What skills does this NAND Design Rule Manager role need?
Key skills for this role include Design Rules, PDK, DRC Waivers, Mask Definitions, Program Execution, Process Integration.
How much does a NAND Design Rule Manager at Micron Technology pay?
The employer did not list a salary for this role. Most similar Singapore roles publish their band on the job page.
Is this NAND Design Rule Manager role remote, hybrid, or on-site?
This role is on-site, based in Singapore.
How do I apply for this NAND Design Rule Manager role?
You can apply directly on Micron Technology's careers page. ApplyLah can tailor your résumé and cover letter to this exact role in seconds first.