About this role
Lead the development and release of design rules and PDK deliverables to support advanced 3D NAND high-volume manufacturing. Collaborate across process integration and design teams to manage DRC waivers, mask reviews, and corrective actions for process issues.
Requires a PhD with 5+ years, a Master's with 8+ years, or a Bachelor's with 13+ years of experience in semiconductor process integration or related fields. Proficiency in CAD tools like Cadence Virtuoso and strong knowledge of VLSI silicon processing and 3D NAND components are mandatory.
What they're looking for
PDK DevelopmentDesign Rule Engineering3D NAND TechnologyCadence VirtuosoK2ViewMentor Graphics DRC/RVESemiconductor Device PhysicsVLSI Silicon Processing
Frequently asked questions
What does a E5_MTS_SMTS NAND Design Rule Engineer in Process Integration at Micron Technology do?
Lead the development and release of design rules and PDK deliverables to support advanced 3D NAND high-volume manufacturing. Collaborate across process integration and design teams to manage DRC waivers, mask reviews, and corrective actions for process issues. Requires a PhD with 5+ years, a Master'…
What skills does this E5_MTS_SMTS NAND Design Rule Engineer in Process Integration role need?
Key skills for this role include PDK Development, Design Rule Engineering, 3D NAND Technology, Cadence Virtuoso, K2View, Mentor Graphics DRC/RVE.
How much does a E5_MTS_SMTS NAND Design Rule Engineer in Process Integration at Micron Technology pay?
The employer did not list a salary for this role. Most similar Singapore roles publish their band on the job page.
Is this E5_MTS_SMTS NAND Design Rule Engineer in Process Integration role remote, hybrid, or on-site?
This role is on-site, based in Singapore.
How do I apply for this E5_MTS_SMTS NAND Design Rule Engineer in Process Integration role?
You can apply directly on Micron Technology's careers page. ApplyLah can tailor your résumé and cover letter to this exact role in seconds first.