About this role
PVH seeks a senior server silicon design engineer to lead analog design for complex IPs used in data center CPUs. The role requires deep expertise in PLL, ADC/DAC, DC/DC, LDO, and related analog IP blocks, and will involve end-to-end design from definition through production in advanced nodes. The ideal candidate has 5 years of analog/mixed signal experience, strong modeling/simulation skills, and hands-on Cadence tool proficiency, with supervision of layout tasks. J-18808-Ljbffr
Frequently asked questions
What does a Lead Analog/Mixed-Signal Design Engineer for SoC IPs at PVH do?
PVH seeks a senior server silicon design engineer to lead analog design for complex IPs used in data center CPUs. The role requires deep expertise in PLL, ADC/DAC, DC/DC, LDO, and related analog IP blocks, and will involve end-to-end design from definition through production in advanced nodes. The i…
How much does a Lead Analog/Mixed-Signal Design Engineer for SoC IPs at PVH pay?
This role lists a salary of S$120 – S$180 per month.
Is this Lead Analog/Mixed-Signal Design Engineer for SoC IPs role remote, hybrid, or on-site?
The listing is based in Singapore. Check the posting for remote or hybrid options.
How do I apply for this Lead Analog/Mixed-Signal Design Engineer for SoC IPs role?
You can apply directly on PVH 's careers page. ApplyLah can tailor your résumé and cover letter to this exact role in seconds first.