Physical Design Engineer – Singapore (Tapeout & PPA)

PVH Singapore's Silicon Platform Team leads core R&D middleware for chip development, covering logic synthesis, DFT, backend design, and STA/Power integrity. The team collaborates closely with front-end chip teams to drive R&D progress and mass production readiness. The role focuses on block/chip level physical design and collaboration with foundries through tapeout, mass production, packaging and testing. Fluency in English and 3 years APR experience are preferred. J-18808-Ljbffr