About this role
PVH is seeking an experienced RTL engineer to develop synthesizable RTL using Verilog/SystemVerilog for high-performance DSP and optical networking applications. You will translate architectural specs into efficient micro-architectures, own RTL development from specification to tapeout, and collaborate across multiple design teams. The role emphasizes high-speed, low-latency digital logic design, collaboration for design reviews, and mentoring junior engineers. J-18808-Ljbffr
Frequently asked questions
What does a RTL Design Engineer - High-Performance DSP and Networking at PVH do?
PVH is seeking an experienced RTL engineer to develop synthesizable RTL using Verilog/SystemVerilog for high-performance DSP and optical networking applications. You will translate architectural specs into efficient micro-architectures, own RTL development from specification to tapeout, and collabor…
How much does a RTL Design Engineer - High-Performance DSP and Networking at PVH pay?
This role lists a salary of S$100 – S$180 per month.
Is this RTL Design Engineer - High-Performance DSP and Networking role remote, hybrid, or on-site?
The listing is based in Singapore. Check the posting for remote or hybrid options.
How do I apply for this RTL Design Engineer - High-Performance DSP and Networking role?
You can apply directly on PVH 's careers page. ApplyLah can tailor your résumé and cover letter to this exact role in seconds first.