About this role
Develop and execute verification plans for SoC/IP blocks and mixed-signal designs using SystemVerilog and UVM. Collaborate with RTL, architecture, and firmware teams to debug failures and improve verification methodologies.
Requires a BS/MS in Electrical or Computer Engineering with 5-10+ years of verification experience. Proficiency in SystemVerilog, UVM, and scripting languages like Python or Perl is essential.
What they're looking for
SystemVerilogUVMRTL SimulationFunctional CoverageSVAPythonPerlTCL
Frequently asked questions
What does a Associate Staff Design Verification Engineer at Silicon Labs do?
Develop and execute verification plans for SoC/IP blocks and mixed-signal designs using SystemVerilog and UVM. Collaborate with RTL, architecture, and firmware teams to debug failures and improve verification methodologies. Requires a BS/MS in Electrical or Computer Engineering with 5-10+ years of v…
What skills does this Associate Staff Design Verification Engineer role need?
Key skills for this role include SystemVerilog, UVM, RTL Simulation, Functional Coverage, SVA, Python.
How much does a Associate Staff Design Verification Engineer at Silicon Labs pay?
The employer did not list a salary for this role. Most similar Singapore roles publish their band on the job page.
Is this Associate Staff Design Verification Engineer role remote, hybrid, or on-site?
This role is hybrid, based in Singapore.
How do I apply for this Associate Staff Design Verification Engineer role?
You can apply directly on Silicon Labs's careers page. ApplyLah can tailor your résumé and cover letter to this exact role in seconds first.