Senior Phy Design Engineer

Key Responsibilities: 1. Circuit Design & Development. Design high-speed analog circuits for DDR PHY interfaces (DDR4/DDR5/LPDDR5/6). Key modules: PLLs, DLLs, TX/RX channels, ODT (On-Die Termination), equalizers (CTLE/DFE), voltage regulators. Optimize power, performance, area (PPA), and signal integrity (SI). 2. Signal/Power Integrity (SI/PI) Analysis. Model and simulate channel losses, crosstalk, jitter, and eye diagrams. Ensure compliance with JEDEC standards (e.g., DDR5-6400 MT/s). Design impedance-matching networks and noise-suppression circuits. 3. Process Technology Adaptation. Implement designs in advanced nodes (FinFET, 7nm/5nm and below). Address PVT (Process-Voltage-Temperature) variations and reliability challenges (TDDB, EM/IR). Collaborate with layout engineers on floor planning, matching, and parasitic extraction. 4. Validation & Testing. Develop test plans for lab characterization and ATE (Automated Test Equipment). Debug silicon failures using oscilloscopes, BERTs, and protocol analyzers. Perform shmoo plotting, margin analysis, and yield improvement. 5. Cross-Functional Collaboration. Work with digital design, verification, and firmware teams for PHY integration. Support package/PCB teams on SI/PI optimization. Document design specs, simulation reports, and test results. Required Qualifications: 1. Bachelor's degree or above in Electrical and Electronic Engineering (EEE). 2. With more than 8 years relevant experience in similar field in semiconductor industry. 3. Technical Skills: Proficiency in EDA tools: Cadence Virtuoso, Spectre, HSPICE, ADS, EMX. Hands-on experience with DDR protocols (JEDEC DDR4/5, LPDDR5/6). Strong knowledge of analog fundamentals: noise analysis, stability, feedback systems. Experience in high-speed I/O design (>6.4 Gbps for DDR5). 4. Preferred Expertise: Design tape-out experience in FinFET/SOI technologies. Familiarity with SerDes, HBM, or other high-speed interfaces. Scripting skills: Python, MATLAB, Verilog-A/AMS.