Staff Analog Mixed-Signal Circuit Design Engineer

Key Responsibilities: 1. Advanced CMOS PLL architecture definition, device level design and verification. 2. Lead system spec to production design cycle. 3. Lead layout implementation and testing. 4. Achieve industry leading jitter, noise and spur performance. 5. Architecture and system level design. Architecture choice-based noise/jitter/spur spec (optimal architecture - integer/Fraction/SS/MDLL etc.) Derive system parameters (Loop BW, Noise margin, noise TF, spur reduction), system verification through behavioral to transistor model (Verilog-A, MATLAB, SpectreRF. 6. Circuit design. Design and verify key components: LC VCO, R-VCO, MMD, PFD, CP, LF, frac-N SDM, calibration engine and LDO. Noise optimization (sub 100fs RMS jitter), wide tuning range (multi-GHz), low power and PVT robustness. Calibration logic (ADC based VCO gain tracking, background spur reduction, DTC linearization). 7. Layout and physical implementation. Lead layout floor planning, strategize noise reduciton through guardring, sensitive nodes, shielding. Layout best practices - matching, isolation. EMIR. 8. Chip verification and tuning. Automation using LabView, Python. PN, jitter, lock time, spur, temp sensitivity analysis through oscilloscope, spectrum analyzer, signal source and PN analyzer. 9. Documentation and IP Re-use. Authoring design spec, test plan, results report and app note. PLL IP solution package including behavioral model, PDK and testing platform. Required Qualifications: Bachelors / Masters / Phd Degree in Electronics Engineering, Micro-electronics or a related field. With more than 8 years relevant experience in similar field in semiconductor industry. Master level custom design / RF design flow experience. Skilled RF/mixed-signal lab equipment: high BW oscilloscope, signal source and VNA, spectrum analyzer, PN tester and probe station. Deep understanding of phase noise, jitter, VCO push/pull, power supply sensitivity, LO leakage and spur mechanisms. Python, MATLAB, SKILL scripting data analytics and testing automation skills. Strong communication skills, mentoring junior engineers.