Technical Manager (Design Verification)

Technical Manager – Design Verification (IC Physical Design) Location: Singapore Employment Type: Full-Time Industry: Semiconductor / ASIC / SoC Design Lead the Physical Design of Next-Generation Semiconductor Innovations Are you an experienced IC Physical Design professional with a proven track record of delivering successful SoC tapeouts? We are looking for a Technical Manager – Design Verification (IC Physical Design) to lead complex chip implementation projects using cutting-edge process technologies . This is an exciting opportunity to work on advanced semiconductor designs at 6nm, 4nm, 3nm, and beyond, driving full-chip implementation from RTL to GDSII while collaborating with world-class engineering teams. Key Responsibilities As a Technical Manager, you will play a critical leadership role in the successful execution of advanced SoC physical design projects by: Leading IC Physical Design implementation from RTL to GDSII across advanced technology nodes (6nm, 4nm, 3nm and below). Coordinating physical design activities across 10+ design blocks, covering: Logic Synthesis Automatic Place & Route (APR) Physical Verification (PV) Providing technical guidance to block owners and resolving critical implementation challenges. Managing full-chip implementation for highly complex hierarchical SoCs containing: Over 20 million instances More than 1,000 memory macros Driving floor planning, partitioning, chip assembly, and full-chip integration. Acting as the Physical Design Program Manager by coordinating closely with Front-End, Design Verification, DFT, Timing, and Signoff teams. Managing project schedules, risk mitigation, and execution to achieve successful tapeout with the highest quality standards. Requirements Required Qualifications Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related discipline. Extensive experience in IC Physical Design with a successful tapeout track record. Strong understanding of advanced semiconductor implementation flows from RTL to GDSII. Hands-on experience with: Floorplanning Placement & Routing Physical Verification Timing Closure Chip Assembly Hierarchical SoC implementation Experience leading complex SoC projects and coordinating cross-functional engineering teams. Strong knowledge of UNIX/Linux operating environments. Programming or scripting proficiency in at least one of the following: Python Tcl Perl C/C++ Preferred Skills Experience working on advanced technology nodes (6nm, 4nm, 3nm, or below). Strong project leadership and stakeholder management skills. Excellent problem-solving and technical decision-making capabilities. Ability to coordinate multiple engineering teams to resolve critical project issues. Strong communication and interpersonal skills within global engineering organizations. Why Join Us? Work on cutting-edge AI and high-performance computing SoCs. Lead complex semiconductor projects using the latest process technologies. Collaborate with globally recognized engineering experts. Drive products from concept through successful silicon tapeout. Competitive compensation, excellent career progression, and opportunities for technical leadership. Be part of an innovative environment shaping the future of semiconductor technology. Apply Today If you are passionate about advanced IC Physical Design and have the leadership experience to drive complex SoC projects to successful tapeout , we would love to hear from you. Take the next step in your semiconductor career and join us in building the next generation of world-class silicon solutions.