Senior Principal Soc Design Engineer

Job Responsibilities:- Develop robust and reusable Code and ensure VHDL or Verilog implementation enables readiness for Verification, Synthesis, DfT and Low Power Insertion Pre-silicon RTL Codingof block, IP and top level SOC Integration Develop reusable RTL Code, using Generic and Modular Coding Style Contribute to verification plan from specification and in coordination with architects Collaborate on Timing constraints, Testability and Insertion of Low Power Structure such as Powergating, Isolation and Retention Sequential Elements Own Linting, CDC, RDC and collaborate with Verification Team and Physical Design Co-work with Architecture/ Design/Validation/SW teams Own cross functional micro-architecture and implementation and drive issues to closure Job Requirements:- Bachelor Degree or Master's in Electronics Engineering with at least 18 years or more years of working experience Expert in VHDL andVerilog Coding, Front End Design using best-in-class methodology and Micro-architecture Have developed Multi-Milliongates IP and integrated heterogenous complex SoC, including Analog and Mixed Signal IP Participated in Micro-architectureSpecification Familiar with Hardware-Software Partitioning, Multi-CPU and Multi-Core Architecture Deep knowledge and understanding of NoC and multi-layer complex Interconnect Systems Solid verificationskills in problem solving, constrained random testing and debugging Expertise with Code Linting tools and Static Code checker such as Spyglass, Real Intent, etc Expertise in IP-XACT,Connectivity Checks, Register Interfaces and RTL Assembly Tools Programming experience in C/C++/assembly/SVA Experience of working with ARM and ARM Eco-system, AXI, AHB, SERDES systems, communication peripherals(UART, I2C, SPI), power management Experience in WiFi/DOCSIS/Ethernet/DSP/DDR is a plus Setup Automated regressions environment and in general automate repetitive verification tasks to enhance productivity Strong team player and communicator Location: N…