Senior Engineer – Hbm Pe Component Validation

Job Description Key Responsibilities HBM Validation Execution Execute Validation Runs on IQP/ETV materials in a high‑pressure, fast‑paced environment , meeting tight start/finish windows , material utilization plans , and readiness checkpoints . Deliver time‑bound data crunching (log parsing, statistical summaries, anomaly triage) and publish concise, high‑quality summary reports/sightings by agreed TAT (turnaround time) targets. Ensure coverage completeness across MBIST and Mode flows; perform Hot/Cold corners , TSV screen/AQLK , and async timing boundary checks. Platform Expertise Operate and debug programs on SM3/Cobra (MBIST) and Advantest V93K . Support hardware readiness: handler, socket, loadboard, probe card coordination aligned to test intent. Technical Analysis & Verilog Simulation Validate high‑speed I/O (≥10 Gbps); perform eye diagram , jitter , and signal integrity checks under P/V/T corners. Measure IDD power profiles and thermal behavior under realistic stress conditions. Develop/execute Verilog testbenches and simulations to reproduce/triage sightings, correlate bench and platform behavior, and inform content fixes. Data & Automation Review logs, crunch data, and automate workflows using Python/Perl . Maintain documentation in Confluence/Jira and version control in Git/Perforce . Debug & Collaboration Assist in root‑cause analysis and corrective action closure with Design, DV, QA, GQ, TSE . Create and deliver technical presentations; participate in cross‑site meetings for silicon readiness. Artificial Intelligence Using, applying and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision making across projects and teams Minimum Requirements Bachelor’s in Electrical or Computer Engineering (or related). 5+ years in DRAM/HBM/NAND validation or product engineering. At least 2 years of HBM Validation experience. Test platform code development in C/C++ , Python , and APG (Algorithmic Pattern Generator) . Hands‑on experience with MBIST (SM3/Cobra) and Mode (Advantest V93K) testing. Verilog simulation experience (writing testbenches, running sims, interpreting waveforms/logs). Familiarity with high‑speed I/O validation and power/thermal characterization . Proficiency in scripting (Python/Perl) and data analysis tools; strong communication and presentation skills. Preferred Skills Linux programming experience; familiarity with UVM , and version control systems ( Git/SVN ). Comfortable with lab equipment (oscilloscopes, logic analyzers). Experience with CS/QS shmoo targets and async timing coverage . Exposure to DFMEA gap closure and operational excellence practices.