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Principal Engineer Engineer -(Integration Yield Defect))

Vanguard International Semiconductor Singapore Pte. Ltd.

D18 Pasir Ris, TampinesPermanentS$6,000 – S$8,000/mo

Posted 6 Jul 2026

About this role

Job Purpose: To liaise with module engineers on defect excursion control To drive for defect reduction and yield improvement activities Job Description: Supervise YE Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operati Train and certify YE Associate Engineers on recipe creation and defect source knowledge Maintain and enhance internal SOP/OCAP and involve in internal;/external audit Operate FIB/SEM/EDX/OM for inline failure analysis Operate and create recipes in Brightfield, Darkfield and other defect inspection tool Perform partition analysis on defect source and detailed reports on issues Build and develop defect source library. Track inline defect performance by layer/process tool/chamber on weekly basis Perform killer ration analysis Perform defect characterization by process tools Continuous improvement activities on defect reductions with Modules / vendors / equipment team Liaise with process engineers in different modules to troubleshoot for inline defects and defect reduction activities Provide scan support in low yield investigation & co-work with Module/PI/PE on technology & device specific yield enhancement activities Automate daily activities to improve troubleshooting speed of team Responsible for wafer quality to conform to product requirements and have the authority to stop shipment and stop production to correct quality problems Job Requirements: Masters / Degree in Electrical and Electronic Engineering/ Microelectronics Engineering / Material Science / Chemical Engineering / Electronic and Physics 5 – 8 years relevant fab work experience in high volume manufacturing of electronics components in an Front-end semi-conductor industry. Experience in defect analysis and yield enhancement in wafer process. Excellent interpersonal and communication skills with good leadership capability. Team player. Strong analytical skills and able to work under pressure in a fast pace environment, Proficient with MS Power Point, Excel, Excel VBA, PowerBI

What they're looking for

ConstructionFMEAProcess IntegrationElectrical

About Vanguard International Semiconductor Singapore Pte. Ltd.

Industry: Manufacturing

Frequently asked questions

What does a Principal Engineer Engineer -(Integration Yield Defect)) at Vanguard International Semiconductor Singapore Pte. Ltd. do?

Job Purpose: To liaise with module engineers on defect excursion control To drive for defect reduction and yield improvement activities Job Description: Supervise YE Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operati Train and certify YE Associate Engineers on re…

What skills does this Principal Engineer Engineer -(Integration Yield Defect)) role need?

Key skills for this role include Construction, FMEA, Process Integration, Electrical.

How much does a Principal Engineer Engineer -(Integration Yield Defect)) at Vanguard International Semiconductor Singapore Pte. Ltd. pay?

This role lists a salary of S$6,000 – S$8,000 per month.

Is this Principal Engineer Engineer -(Integration Yield Defect)) role remote, hybrid, or on-site?

The listing is based in D18 Pasir Ris, Tampines. Check the posting for remote or hybrid options.

How do I apply for this Principal Engineer Engineer -(Integration Yield Defect)) role?

You can apply directly on Vanguard International Semiconductor Singapore Pte. Ltd.'s careers page. ApplyLah can tailor your résumé and cover letter to this exact role in seconds first.