Senior Design Engineer (Cleanroom)

Location: Woodlands Working Hours: 5.5 days per week (Mon to Fri: 8:00 AM – 5:30 PM, Sat: 8:00 AM – 12:30 PM) Willingness to commit to extended hours Job Responsibilities Lead cleanroom design and planning for semiconductor projects Develop cleanroom layouts, zoning, airflow, and pressure control concepts Coordinate cleanroom requirements with HVAC, electrical, and process teams Review cleanroom materials, finishes, and system specifications Support installation, testing, and commissioning of cleanroom systems Ensure contamination control and cleanroom protocols are met Resolve design and site-related cleanroom issues Liaise with clients, consultants, and contractors Ensure compliance with cleanroom standards and Singapore regulations Mentor junior engineers and designers Any other ad-hoc duties as assigned Requirements Bachelor’s Degree in Mechanical, Chemical, or related Engineering field Minimum 5 years of cleanroom or semiconductor facility design experience Strong understanding of contamination control and cleanroom standards Proficient in AutoCAD or Revit Strong coordination and leadership capabilities Proficiency in Mandarin is required to liaise with Mandarin-speaking stakeholders, suppliers and project counterparts.